IP blocks
Our equipment for circuits to meet your demands
RISC-V Core
64-bit
Command system in line with RISC-V Instruction Set Manual Volume I: User-level ISA Version 1
FPGA verification as part of navigation satellite reciever
Verified in ASIC (180 nm, CMOSFET "Micron") as part of single-core SoC
Full dev toolkit and debug printed circuit
Programming model for quick prototyping of new solutions
About
RISC-V is an open standard instruction set architecture
The instruction set specification defines 32-bit and 64-bit address space variants. The specification includes a description of a 128-bit flat address space variant, as an extrapolation of 32 and 64 bit variants, but the 128-bit ISA remains "not frozen" intentionally, because there is yet so little practical experience with such large memory systems.
SRAM
AXI4 to memory bridge with SECDEC and exclusive access support
AXI interconnect
System Interconnect with support of AXI3/ AXI4/ AHB/ APB interfaces
SPI master interface
SPI master controller with AXI4 interface
I2C master interface
I2C master controller with AXI4 interface
DMA controller
• AMBA APB interface for control/ status register access
• Two AXI4 master interfaces: for data transfers and for scatter gather tasks access
• Scatter gater tasks (descriptors) can be stored in any system writable memory locations
• FIXED and INCR AXI4 burst types supported
GPIO with APB/AXI interface
GPIO controller with AXI4/ APB interfaces
UART interface
UART controller with AXI4/ APB interfaces
GPT
General purpose timer with AXI4/ APB interfaces
Analog IP
PLL
PLL with frequency up to 5 GHz (TSMC 28 HPC+)
LVDS RX
LVDS RX up to 600MT/s (TSMC 28 HPC+)
Interfaces under development
• DDR4/LPDDR4 CTRL
• DDR4/LPDDR4 PHY
• PCIe CTRL
• Ethernet 1/10G CTRL
• USB 3.0 CTRL
• USB/PCIe/Ethernet Multi PHY
IP Blocks